• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    Method and apparatus for converting a virtual address contained in an instruction into a real memory access address, when the stored data are organized in functional sets, the latter being divided into segments. Conversion is performed by means of a functional set number register 12, a segment label table 7, a plurality of base registers 4, and a base register updating device. The invention is applicable to data processing systems.
    公开号:SU1162377A3
    申请号:SU792786748
    申请日:1979-07-16
    公开日:1985-06-15
    发明作者:Мари Аллэн Жак；Куртель Даниель；Жубер Жан-Луи；Видонн Жан-Пьер
    申请人:Ле Матерьель Телефоник (Фирма)；
    IPC主号:
    专利说明:

    respectively, with the control inputs of the base register node and the central memory, the output of the second element AND of the access control unit is connected to the first inputs of the AND elements of the first group and through the elements of the NOT group to the first inputs of the AND elements of the second group, first, second and third groups of inputs the preliminary address register is connected respectively to the output groups of the information address register, the function block number register and the second group of outputs of the virtual address register, the second inputs of the first and second elements The second groups are connected to the corresponding outputs of the central memory, the outputs of the elements And the first group are connected to the corresponding perHctpa data inputs, the outputs of the elements AND the second group are connected to the corresponding data inputs of the node of the basic registers, the input of the logical unit of the formation of the confirmation signal is connected to the input of the logical unit of the device, and in the access control unit, the output of the first element is NOT connected to the .7 input of the second trigger, the clock input of which is connected to the first output of the first delay line, in The op and the third outputs of which are connected respectively to the first inputs of the first element OR and the fourth element AND, the outputs of the second trigger are connected to the second input of the fourth element AND, the first inputs of the first and third elements AND, the second element OR, and through the second element NOT to the second the input of the second element is And the first
    the output of the second delay line is connected to the second input of the first element AND, the second output of the second delay line is connected to the force input of the second trigger, the second inputs of the second OR element and the first AND element, the third output of the second delay line of the connections to the second input of the first OR element, the outputs of the first and The second IDN elements are connected respectively to the clock input and the force input of the first trigger, the output of the fourth element I is connected to the control input of the multiplexer, K-input of the second trigger and D-input of the first ggera connected respectively to inputs of logic zero and logic unit of the device,
    2. The device according to claim 1, wherein the confirmation signal block contains a decoder, a group of elements, a trigger group and a multiplexer, the group of address inputs of the block is connected to the group of inputs of the decoder and the group the control inputs of the multiplexer, the output of which is the output of the block, the outputs of the group triggers are connected to the corresponding w information inputs of the multiplexer, the outputs of the elements AND of the group are connected to the clock inputs of the group triggers, the forcing inputs of which are connected to the input Force fo8ani unit, a control input coupled to a first input E edementov AND group whose second inputs are connected to outputs sootvetstvuyutsimi deshi Ator, logic block input unit connected to the input depifratora uB -vhodaki triggers group.
    This invention relates to devices for converting a virtual address to a real address.
    A virtual address is an address that is contained in a program command and which should be modified to access information expressed in
    word in the central memory, while using the real address provides direct access.
    By central memory is meant a storage device, which, in contrast to or auxiliary memory, contains information
    which is directly accessible from the central unit of the computing device.
    A device for dynamic address translation is known, comprising three registers, a memory block, three comparison circuits, a switch, a generator, a control unit, AND, OR 0 elements.
    The disadvantage of the device is low speed.
    Closest to the invention is a device for converting a virtual address into a real address for a real-time data processing system in which programs are distributed among numbered functional groups, each functional group being in turn divided into segments defined by the same number of descriptors 2j.
    The method of dividing a program into segments or segmentation makes it possible to reduce the dimensions of the central memory, producing at a given moment only a segment of the central memory, the program of which must be used at a given moment.
    The known conversion device uses the register of the functional group number, the segment descriptor table localized in the central memory of the data processing system, and the registers, called the base ones, each of which is intended to store the segment descriptor, and the system of the registers used to store the segment descriptors required for functional group
    The disadvantage of this device due to the relatively high time of the operation.
    The purpose of the invention is to increase speed.
    The goal is achieved by having a device for converting a virtual address to a real address containing a central memory, a base register node and an adder, a virtual address register, a function register number register, an information address register, a command register, a data register, two command decoders, and the delay line whose input is connected to
    the output of the first command decryptor, the group of inputs of which is connected to the group of outputs of the command register and to the group of inputs of the second decoder {eator
    5 commands, the first group of inputs of the adder is connected to the group of outputs of the base register node, the second group of inputs of the adder is connected to the first group of inputs of the register of the virtual address, the group of address inputs of the node of the basic registers connected to the second group of outputs of the register of the virtual address contains. a signal shaping unit confirming the date
    addresses, two groups of elements AND, a group of elements NOT and a control unit. an access containing two delay lines, two NOT elements, two flip-flops, two OR elements, four AND elements, a multiplexer, the group of address inputs of the confirmation signal generating unit is connected to the second group of outputs of the real-time address register, the force input signal of the confirmation signal generating unit is connected to the output of the second decoder, the control input of the confirmation signal generating unit is connected to the output of the first element AND of the access control unit, the input of the first element of which is NOT connected to the output b the formation of the confirmation signal, the first group of data inputs of the multiplexer of the access control unit is connected to the group of outputs of the adder, the second group of data inputs of the adder block
    access control is connected to a group of outputs of the preliminary address register, a group of data outputs of a multiplexer access control unit is connected to a group of address inputs of the central memory, the input of the first delay line of the access control block is connected to the output of the first decoder, the input of the second delay line of the access control block is connected to the first input of the second element I of the access control unit and with the output of the delay bar, the outputs of the third element I and the first trigger of the access control block are connected respectively naturally with the control inputs of the base register node
    and the central memory of the output of the second element And the access control unit is connected to the first inputs of the elements AND of the first group and through the elements of the NOT group to the first inputs of the elements AND of the second group, the first, second and third groups of inputs of the preliminary address register are connected respectively to the output groups of the address register information, the register of the functional unit number and the second group of outputs of the virtual address register, the second inputs of the AND elements of the first and second groups are connected to the corresponding outputs of the central memory and, the outputs of the elements of the first group are connected to the corresponding inputs of the register data, the outputs of the elements of the second group are connected to the corresponding data inputs of the node of the basic registers, the input of the logical unit of the confirmation signal generating unit is connected to the input of the logical unit of the device j in the access control unit - ment is NOT connected to the 3-input of the second trigger, the clock input of which is connected to the first input of the first delay line, the second and third outputs of which are connected respectively to ne the first inputs of the first OR element and the fourth element AND, the output of the second trigger is connected to the second input of the fourth element AND, the first inputs of the first and third elements AND, the second element 1-1LI and through the second element NOT to the second input of the second element AND, the first output of the second the delay line is connected to the second input of the first element AND, the second output of the second delay line is connected to the force input of the second trigger, the second inputs of the second OR element and the first AND element, the third lead of the second delay line is connected to the second the input of the first element OR, the outputs of the first and second elements OR are connected to the clock input and the forcing input of the first trigger, the output of the fourth element AND cc5 is connected to the control input of the multiplexer, the K input of the second trigger and D are the input of the first trigger respectively the inputs of logical zero and logical unit1№1 devices.
    In addition, the confirmation signal generating unit contains the decoder, the rpyitny elements AND, the trigger group and the multiplexer, the group of address inputs of the block connected to the group of inputs of the decoder and the group of control inputs of the multiplexer whose output is the block output, the outputs of trigger groups of the group connected to the corresponding information input multiplexer, outputs of AND elements
    the groups are connected to the clock inputs of the group triggers, the forcing inputs of which are connected to the forsyrope input of the block, the control input of jcoToporo is connected to the first
    5 inputs of elements AND groups, the second inputs of which are connected to the corresponding outputs of the decoder, the input of the logical unit of the block is connected to the input of the decoder and D-inputs
    O group triggers.
    Fig. 1 shows a block diagram of the device; in Fig. 2, the same, a confirmation signal generating unit; 5 in FIG. 3 is the same as the access control unit.
    The device contains an address converter 1, a central unit 2, a central memory .3, a base register node 4, an adder 5, a preliminary address register 6, a segment descriptor table 7, a base register designator 8, a baseline signal generation unit 9, block 10 access control, virtual address register 11, function block nrmer register 12, information address register 13, second decoder 14, data register 15, command register 16, first decoder 17, delay line 18, first and second element ntov And 19, 20, the group of elements is NOT 21.
    Block 9 contains a decoder 22, a group of elements And 23, a group of triggers 24 and multiplexer 25.
    Block 10 contains two delay lines 26 and 27, two elements NOT 28 and 29, two triggers 30 and 31, two elements OR 32 and 33, four AND elements 34-37 and multiplexer 38, a segment descriptor acknowledgment detection circuit 39, circuit 40 start up access to the central memory and circuit 41
     data confirmation, input terminal 42, output terminals 43, 44 and 45, input terminal 46, output terminals 47-49.
    The address transformer 1 contains a node 4, in which a partial table of functional segment segments descriptors is stored for storage in the execution process, an adder 5, which is used to form a real address, i.e. central memory addresses during normal access during command execution, and register 6 to generate a preliminary address, i.e. the central memory addresses during the preliminary Access to the table of descriptor segments 7, found 11 (it is in the central memory.
    According to the invention, the address transformer 1 also contains an organizer 8 for designating basic register registers, which in its outline contains block 9, which contains a table of confirmation indicators relative to the functional group in the process of executing the descriptors of the segments contained in the basic registers, and block 10 access control to the central memory, allowing control of either normal access or pre-access to the table of descriptors of the mattemata, followed by normal access depending on bridges of whether or not the base descriptor of the segment descriptor, which is defined in the command during its execution, is present in the base registers, with
    The virtual address comes from one of the registers 11 of the virtual address 11 located in the central unit. This register {) contains the segment number in the process of execution (Sa-S binary elements) and the offset inside the segment (binary NLo-NL elements). The command operation code (binary OP -Off) comes from the register 16 of the command located in the central unit. The number of the functional group in the process of execution (binary elements E # -Eg) comes from the register 12 of the number of the functional group located in the central unit. The starting address of the table of descriptors of seg mates (binary elements BO-Bfl) comes from register 13 located in the central block.
    In the expression in the process of execution, the term execution implies all operations performed starting with loading a command into the control register. The adder 5 form # 1 real address (binary elements ARg-ARj ;,) ,. starting with the segment descriptor (binary elements BSo-BSjj) coming from the base registers, and the offset in the segment (binary elements NLp-NLg) generated by the register 11. Register 6 generates a preliminary address (binary elements AF j-APj) by placing a row of segment, functional group number and starting address of the table of segment descriptors.
    The number of binary elements for encoding various signals has been chosen only as an example of a more concise illustration of the invention. Any change of this number is possible, without departing from the scope of the invention.
    If the command operation code indicates a command different from the functional group change command, then the central unit sprinkles the DM signal about the access to the central memory in block 10. In block 10, it should first of all check whether the descriptor is present in the basic registers the process of execution. For this reason, the segment number during the execution is fed to the input of block 9, KOTopbtff in this case, in block 10, VDS confirms the opening of the segment.
    If the VDS signal indicates that the segment descriptor is present in the base registers during execution, i.e. if there is confirmation of this descriptor, then a normal access command is issued. For this, the segment number in the execution process is fed to the input of the basic registers, which in this case give the descriptor base to the adder 5. Block 10, which receives the real address and tentative address, in this case case, selects the real address and sprinkles the DCM trigger trigger signal into the central memory. The address of the central memory (binary elements) is equal to the real address, while the data read from the real memory (binary elements DOMo-BOMj) can be taken into account by the central unit. To do this, the EM response of the memory sprinkled with the central memory in block 10 is converted by block 10 into a signal DV to confirm the data received in the central block,
    Conversely, if the VDS signal indicates that the segment descriptor is not present in the base registers during execution, then a pre-access command is given to the segment descriptor table. For this, block 10 selects a pre-address and sends an access start DCM signal to the central memory to the central memory. The central memory address is equal to the preliminary address, and block 10: assigns the DV signal to the central unit and manages the DOMo-DOMjf data records in the base registers by feeding the write registers in the base registers to the base registers in the base registers. Then block 10 sprinkles block 9 into an entry control signal EIV in the table of confirmation indicators. The named signal is intended to change the state of the confirmation of the segment descriptor during execution. In this case, the real access control can be performed, and the operand is the same as already described.
    If the operad-sh command code indicates one of the functional group change commands, then the decoder of the operation code causes the system state of the confirmation indicators of block 9 to change by means of the ETIV signal, while changing the contents of register 12 of the functional group number.
    Referring to Fig. 1, the segment number is encoded using five binary elements (So-S4). In this case, the maximum number of n segments of the functional group is 32, and the table of confirmation indicators (Fig. 2) contains 32 D-type indicator triggers,
    A readout circuit from a table of confirmation indicators is formed by a readout multiplexer 25 having 32 inputs connected to the outputs O of indicator triggers, the multiplexer being controlled by the segment number in the execution process (binary elements;; SB-5f). The output of the VDS multiplexer 25 is equal to the signal emitted by the indicator trigger, the number of which coincides with the number of the segment.
    Fia inputs 1) indicator triggers 30 are supported by a logical 5 level one.
    The recording circuit of the indicator triggers is formed by a group of 32 elements. And one input of each of these elements is powered by the record control signal EIV in the table of confirmation indicators, and the output is connected to the input of the clock device SC of one of the indicator triggers. At one entrance decrypt5. Logger 22 maintains a logic level one, and the said decoder is controlled by binary elements So + S. .. To the input CL forcing 32 indicator triggers
    0 with a logic level of zero, the signal ETIV comes from the output of the decoder 14.
    When a request is received for accessing the DM signal to the central memory
    Block 10 checks the VDS signal. If the VDS signal has a logic level of one, it means that the base registers contain a segment descriptor in the execution process,
    in this case, normal access can be made. If the VDS signal has a logic level of zero, block 10 issues a command to pre-access the segment descriptor table, and if the descriptor is present in the base registers, sprinkle the EIV signal with a logic level one into the confirmation indicator table. In this case, the named signal is EIV, acting together with the decoder 22; allows activating the indicator trigger whose number corresponds to the segment number in the execution process, i.e. exit Oh
    This trigger goes to logical unit one.
    It can be seen from FIG. 3 that the access control unit contains the multiplexer 38 for addressing the central memory, the sequence generator formed by the first delay line 26 and the second delay line 27, the segment descriptor acknowledgment detection circuit 39, the multiplexer 38 control And 37, the control element 36 recording in the base registers, control element 34 and writing in the table of confirmation indicators, a startup circuit 40 for accessing the central memory and a circuit 4 for confirming data read from the central memory. The first delay line 36 is equipped; the input terminal 42, which is the first input terminal of the sequence generator, is supplied with a DM request for access to the central memory, the output terminal 43, which is the first output terminal of the sequence generator and with which the first output signal T is removed , | a sequence generator, output terminal 44, which is the second output sequence generator and which detects the second output signal of the sequence generator T2; output terminal 45, which is the third output glue of the sequencer and from which the third output T of the sequencer of the sequencer is removed. The second delay line 27 is equipped with an input terminal 46, which is the second input terminal of the sequence generator and to which the central memory response signal VM is supplied; output terminal 47, which is the fourth output terminal of the sequencer and c. which is the fourth output signal of the sequence generator 14, the output terminal 48, which is the fifth output terminal of the sequence generator and from which the fifth output signal T of the sequence generator is output; output terminal 49., which is the sixth output terminal of the sequence builder, and from which the sixth output signal of the sequence builder is detected. Confirmation detection circuit 39 is formed by SC-type confirmation detection trigger 30, at input 3 of which a VDS signal is received, inverted by an HE element 28, while logic level Z is maintained at input K of the named trigger, and triggering input CL is supported. the level is zero, the fifth output signal T 771 arrives. the sequence generator, the first output signal T for the fifth sequence signal is sent to the clock input of the CS, and the DTV detection signal is output from the output Q audio, input signals of the multiplexer 38 are formed, on the one hand, the real address (binary elements ARij-ARj), vschavaemym cyiwaTorom 5 and, on the other hand, preliminary location (binary elements ARfj -ARj), issued register 6. Under the influence of the signal. The SAD assigned by AND 37, multiplexer 38, absorbs the central memory address signal (binary AMg-AM5). The central memory access start circuit 40 is formed by a D-type trigger 31, at the input D of which a logic level is maintained one, the clock input SC of which receives the output signal from the OR 32 element between the second and sixth output of the sequence generator, to the input CL forcing of the named trigger with a logic level zero, the output signal from the element OR 33 between the DTV signal and the fifth output signal Tj of the sequence generator comes, and the trigger DCM signal is removed from the output Q of the trigger PA to the central -,. memory The confirmation circuit 41 reads data from the central memory formed by element AND 35 between the signal RM arriving at the second input terminal of the sequence generator and the signal RM inverted by the element HE 29. I In response to the first input pulse of the sequence generator, i.e. on a request for access to the central memory received from the central unit, the signals T, T. and T represent the first, second and third output pulse of the sequence generator, respectively, which are delayed relative to one another and with respect to the third output a pulse shaper sequence, wherein the delay time is determined by the first delay line 26. The first pulse shaper of the sequence activates a confirmation detection trigger 30. I If the segment descriptor is not present in the base registers during execution, i.e. if the VDS signal is at the logic level zero, then the DTV signal goes to the logic level one. When a sequence of a second output pulse is added to the .wlgcode n1) sequence organizer, three germs 31 of the memory access start are activated, thanks to which preliminary access to the table is launched, segment descriptors with a preliminary address generated by multiplexer 38 in response to the third output pulse of the driver ti. After pre-access, the memory response signal PM is a pulse, which is sent by the BTOpbiM to the input pulse of the sequence generator. Due to the fact that the DTV signal is at the logical level of the unit, the confirmation circuit 41 prohibits the transmission of the DV signal to the central unit. In response to this second input pulse, the signals T, Tg- and Tg are received, which are the fourth, fifth, respectively. and the poles by the output pulses of the sequence generator, following with a delay one relative to the other and relative to the second output pulse, the duration, the delay being determined by the second line delay 27, When a fourth output pulse arrives from the The sequence sequencer EI signal is active and controls the Descriptor Record in the base registers. As the fifth output pulse arrives from the sequence generator, the EIV signal is active and controls the transition of the acknowledgment indicator to the logic level one. At the same time, when the fifth output pulse arrives from the sequence generator, the DTV signal goes to the zero level. With the sixth output pulse of the sequencer, the trigger trigger 31 is activated, thereby triggering normal access to the central memory with the real address generated by multiplexer 38. After real access, the PM signal is an impulse. Due to the fact that the DTV signal is at the logical zero level, the circuit 41 confirms that the signal DV is being supplied to the central unit. If the segment descriptor is present in the base registers in the execution process, i.e. Since the DTV signal is at the logical one level, then at the first output pulse of the sequence generator, the DTV signal remains at the logical zero level. At the second output pulse of the sequencer, trigger trigger 31 is activated, so that normal access is triggered with the real address generated by multiplexer 38. Due to the DTV signal being at a logic level zero, the acknowledgment circuit 41 triggers the Signal. to the central unit. Thus, it can be seen that the designation of base registers is carried out automatically, i.e. without the intervention of the programmer, since the shaper of the command for designating the basic registers is fully implemented on the cabled logic circuits. On the other hand, it can be seen that the above designation of the basic registers is carried out upon request by means of an indicator table confirming, t, e. as necessary, in contrast to the permanent notation, taK as segment descriptors, not used in the same functional group, do not enter basic registers. Thus, the data processing speed reached; thanks to the use of such a device, the designation of basic registers, much higher than the speed achieved when using the super-spacing program. Automatic marking, which is also carried out on request, can also be done using an automatic firmware compiler instead of cabled automatic installation.
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    权利要求:
    Claims (2)
    [1]
    1. DEVICE FOR CONVERTING A VIRTUAL ADDRESS TO A REAL ADDRESS, containing central memory, a base register node, and an adder, a virtual address register, a function block number register, an information address register, an instruction register, a data register, two instruction decoders and a delay line whose input connected to the output of the first command decoder, the group of inputs of which is connected to the group of outputs of the command register and to the group of inputs of the second command decoder, the first group of inputs of the switch is connected to the group of outputs evil base registers, the second group of inputs of the adder soedinena- with the first group of register outputs a virtual address, the group address inputs of the base registers node coupled to a second group of register outputs a virtual address, otlichayusche- i s e c in that, in order to increase performance, it contains confirmation signal generation unit, preliminary address register, two groups of AND elements, a group of elements NOT and an access control unit containing two delay lines, two NOT elements, two triggers, two OR elements, four elements And she and the multiplexer; moreover, the group of address inputs of the confirmation signal generating unit is connected to the second group of outputs of the virtual address register, the forcing input of the confirmation signal generating unit is connected to the output of the second decoder, the control input of the confirmation signal generating unit is connected to the output of the first AND element of the access control unit, the input of the first element is NOT . which is connected to the output of the confirmation signal generating unit, the first group of data inputs of the access control unit multiplexer is connected to the group of outputs of the adder, the second group of data inputs of the adder of the access control unit is connected to the group of outputs of the preliminary address register, the data output group of the multiplexer of the access control unit is connected to the group address inputs of the central memory, the input of the first delay line of the access control unit is connected to the output of the first decoder, the input of the second line The access control unit is connected to the first input of the second element AND of the access control unit and to the output of the delay line, the outputs of the third element And of the first trigger of the access control unit are connected respectively to the control inputs of the base register and central memory unit, the output of the second element AND of the access control unit connected to the first inputs of ele-. And the first group and through the elements of the NOT group - with the first inputs of the elements AND of the second group, the first, second and third groups of inputs of the preliminary address register are connected respectively to the output group of the information address register, function block number register and the second group of virtual address register outputs the inputs of the elements of the first and second groups are connected to the corresponding outputs of the central memory, the outputs of the elements of the first group are connected to the corresponding inputs of the data register, the outputs of the element And the second group is connected to the corresponding data inputs of the base register node, the input of the logical unit of the confirmation signal generating unit is connected to the input of the logical unit of the device, and in the access control unit the output of the first element is NOT connected to the 7th input of the second trigger, the clock input of which is connected to the first the output of the first delay line, the second and third outputs of which are connected respectively to the first inputs of the first OR element and the fourth AND element, the output of the second trigger is connected to the second input of the four the first element And, the first inputs of the first and third elements And, the second element OR and through the second element NOT - with the second input of the second element And, the first output of the second delay line is connected to the second input of the first element And, the second output of the second delay line is connected to the boost input the second trigger, the second inputs of the second OR element and the first AND element, the third output of the second delay line is connected to the second input of the first OR element, the outputs of the first and second OR elements are connected respectively to the clock input and input ohm of forcing the first trigger, the output of the fourth AND element is connected to the control input of the multiplexer, the K-input of the second trigger and the Ό-input of the first trigger are connected respectively to the inputs of logical zero '' and the logical unit of the device.
    [2]
    2. The device according to claim 1, wherein the confirmation signal generating unit comprises a decoder, a group of AND elements, a group of triggers and a multiplexer, wherein the group of address inputs of the block is connected to the group of decoder inputs and the group control inputs of the multiplexer, the output of which is the output of the unit, the outputs of the group triggers are connected to the corresponding information inputs of the multiplexer, the outputs of the elements and groups are connected to the clock inputs of the group triggers, the forcing inputs of which are connected to the input ation unit, the control input coupled to the first inputs of the first group elements, second inputs of which are connected to respective outputs of the decoder, the input logical block units connected to the input of the decoder y.5 -Log triggers group.
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    BE877784A|1979-11-16|
    CA1127317A|1982-07-06|
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    法律状态:
    优先权:
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